Showing posts with label Understanding. Show all posts
Showing posts with label Understanding. Show all posts
Monday, 21 November 2016
Understanding Processor Architecture RISC versus CISC
Popular processor designs can be broadly divided into two categories: Complex Instruction Set Computers (CISC) and Reduced Instruction Set Computers (RISC). The dominant processor in the PC market, Pentium, belongs to the CISC category. However, the recent trend is to use the RISC designs. Even Intel has moved from CISC to RISC design for their 64-bit processor.
CISC systems use complex instructions. For example, adding two integers is considered a simple instruction. But, an instruction that copies an element from one array to another and automatically updates both array subscripts is considered a complex instruction. RISC systems use only simple instructions. Furthermore, RISC systems assume that the required operands are in the processor’s internal registers, not in the main memory. It turns out that characteristics like simple instructions and restrictions like register-based operands not only simplify the processor design but also result in a processor that provides improved application performance.
Several factors contributed to the popularity of CISC in the 1970s. In those days, memory was very expensive and small in capacity. Even in the mid-1970s, the price of a small 16 KB memory was about $500. So there was a need to minimize the amount of memory required to store a program. An implication of this requirement is that each processor instruction must do more, leading to complex instruction set designs. Complex instructions meant complex hardware, which was also expensive. This was a problem processor designers grappled with until Wilkes proposed microprogrammed control in the early 1950s.
Figure 1. The ISA-level architecture can be implemented either directly in hardware or through a microprogrammed control.
A microprogram is a small run-time interpreter that takes the complex instruction and generates a sequence of simple instructions that can be executed by the hardware. Thus the hardware need not be complex. Once it became possible to design such complex processors by using microprogrammed control, designers went crazy and tried to close the semantic gap between the instructions of the processor and high-level languages. This semantic gap refers to the fact that each instruction in a high-level language specifies a lot more work than an instruction in the machine language. Think of a while loop statement in a high-level language such as C, for example. If we have a processor instruction with the while loop semantics, we could just use one machine language instruction. This explains why most CISC designs use microprogrammed control, as shown in Figure 1.
RISC designs, on the other hand, eliminate the microprogram layer and use the hardware to directly execute instructions. Here is another reason why RISC processors can potentially give improved performance. One advantage of using microprogrammed control is that we can implement variations on the basic ISA architecture by simply modifying the microprogram; there is no need to change the underlying hardware. Thus it is possible to come up with cheaper versions as well as high-performance processors for the same family of processors.
References
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| RISC vs. CISC: What is the differences? |
CISC systems use complex instructions. For example, adding two integers is considered a simple instruction. But, an instruction that copies an element from one array to another and automatically updates both array subscripts is considered a complex instruction. RISC systems use only simple instructions. Furthermore, RISC systems assume that the required operands are in the processor’s internal registers, not in the main memory. It turns out that characteristics like simple instructions and restrictions like register-based operands not only simplify the processor design but also result in a processor that provides improved application performance.
Several factors contributed to the popularity of CISC in the 1970s. In those days, memory was very expensive and small in capacity. Even in the mid-1970s, the price of a small 16 KB memory was about $500. So there was a need to minimize the amount of memory required to store a program. An implication of this requirement is that each processor instruction must do more, leading to complex instruction set designs. Complex instructions meant complex hardware, which was also expensive. This was a problem processor designers grappled with until Wilkes proposed microprogrammed control in the early 1950s.
Figure 1. The ISA-level architecture can be implemented either directly in hardware or through a microprogrammed control.
A microprogram is a small run-time interpreter that takes the complex instruction and generates a sequence of simple instructions that can be executed by the hardware. Thus the hardware need not be complex. Once it became possible to design such complex processors by using microprogrammed control, designers went crazy and tried to close the semantic gap between the instructions of the processor and high-level languages. This semantic gap refers to the fact that each instruction in a high-level language specifies a lot more work than an instruction in the machine language. Think of a while loop statement in a high-level language such as C, for example. If we have a processor instruction with the while loop semantics, we could just use one machine language instruction. This explains why most CISC designs use microprogrammed control, as shown in Figure 1.
RISC designs, on the other hand, eliminate the microprogram layer and use the hardware to directly execute instructions. Here is another reason why RISC processors can potentially give improved performance. One advantage of using microprogrammed control is that we can implement variations on the basic ISA architecture by simply modifying the microprogram; there is no need to change the underlying hardware. Thus it is possible to come up with cheaper versions as well as high-performance processors for the same family of processors.
References
- Guide to RISC Processors for Programmers and Engineers by Sivarama P. Dandamudi, Springer (2005), ISBN 0-387-21017-2.
Wednesday, 2 November 2016
Understanding the workings of Vertical Deflection
Vertical deflection parts, serves to provide a sawtooth current to the vertical deflection coil so that horizontal lines are generated by applying localized horizontal deflection from the top of the screen and moves towards the bottom of the screen. Sweeping PAL system has a vertical frequency of 50 Hz and 60 Hz NTSC system. Vertical deflection circuit there are several variation, is in contrast to the horizontal deflection circuit on television almost all the same.
Broadly , the vertical deflection section comprises:
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| Yoke Deflection |
- Vertical oscillator (vertical countdown)
- Ramp generator
- Vertical amplifier drive
- Vertical amplifier-out
- Pum-up (flyback generator)
- Feedback circuit
- Vertical deflection coil
Countdown vertical as the vertical oscillator. Vertical count-down got input from the horizontal frequency count-down and divide in order to obtain the vertical frequency.
In this section there is a circuit called a "vertical window-counter" which serves to automatically adjust the vertical size of the frequency. Without any input video signal, vertical oscillator oscillates at a frequency of approximately 45 to 55Hz free. If then the aircraft received the system PAL video signals, vertical-counter window will lock the vertical oscillator at a frequency of 50Hz. And if a video signal NTSC system will automatically lock the vertical frequency to 60Hz
If for any damage, so the frequency can not be locked, it will cause:
- Picture rolling up if the frequency is lower
- Rolling down the picture if the frequency is higher.
Ramp-generator - vertical pulses from the oscillator is a square, ramp-function generator to change the shape of the signal box into a sawtooth shape. Sawtooth signal shape is determined by the value of resistor-capacitor filter contained in this section.
Vertical count-down circuit and the ramp-generator circuit is in common IC. But there are certain circuits where the ramp generator IC is in the vertical-out, ie aircraft using the TA8690 and TA8445.
Vertical amplifier Drive - serves to amplify the signal before it is fed into the vertical vertical-output amplifier. Circuits generally be one with a vertical power amplifier out.
Vertical power-amplifier Out - vertical sawtooth signal is amplified by this section to be able to supply power to the coil current sawtooth vertical deflection. The working principle of the vertical amplifier-out does not vary much with the audio power-amplifier
Pump Up (flyback generator) - applying localized electron beam vertically from the top to the bottom of the screen. To conduct further re-sweeping the electron beam must be returned with a quick way into the top layer. To do this required a strong pulse but only a moment the so-called vertical-retrace pulse, which pulse is required to establish a higher voltage supply on the vertical-out amplifier.
While doing the sweeping-vertical from the top of the screen to the bottom of the screen vertically-out circuit generally requires a voltage supply of about 25V. And at the vertical-retrace or back from the bottom to the top of the screen quickly takes a larger supply voltage of about 50V. Vertical pump-up circuit is in the vertical IC-out and serves to generate a high voltage at the moment-vertical retrace and require external components consisting of a diode and an Elko.
Vertical-drive circuit, pump-up and reinforcing vertical-out is generally a single IC package in the vertical-out.
There are several types of vertical IC-outs that do not use a pump-up circuit. Instead of the vertical-out requires two kinds of supply Vcc, the supply of low voltage and high voltage supply.
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