Sunday, 26 February 2017
The Nexus 8 or Nexus Android 9 L and 64 bit processor could have these features and design
The Nexus Nexus 8 or 9 remains a mystery and although we saw earlier as might be the design of this new tablet, the latest concept shows us the tablet based on Android L and a 64 bits.
This recreation was created by Vishal Bhanushali and has posted up a video to illustrate what could be the new product from Google.
The Nexus 8 which would be manufactured by HTC would have a soft material at the back to allow it to have a good grip, especially that it would be very thin and light. This rear appears very similar to the rear of the Nexus July 2013.
8 The Nexus runs the latest version of Google's mobile operating system Android Android Lollipop L or (if they end up calling the company), which offers the Material Design (Design Material), as support for 64-bit processors could be Intel or Qualcomm.
Being manufactured by HTC, the Nexus 8 would have the two speakers in the front that are named BoomSound.
According to the creator of this concept, the Nexus 8 would result by the minimalist aspect of L and Android Nexus devices, like the good style that HTC has shown in recent years.
Although this is only a concept, it is very possible that Google present Neuxs 6 and 8 together with Android Nexus L (Lollopop) possibly in October this year. Wait for it to arrive this date to find which is what Google actually has prepared for us.
Monday, 21 November 2016
Understanding Processor Architecture RISC versus CISC
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| RISC vs. CISC: What is the differences? |
CISC systems use complex instructions. For example, adding two integers is considered a simple instruction. But, an instruction that copies an element from one array to another and automatically updates both array subscripts is considered a complex instruction. RISC systems use only simple instructions. Furthermore, RISC systems assume that the required operands are in the processor’s internal registers, not in the main memory. It turns out that characteristics like simple instructions and restrictions like register-based operands not only simplify the processor design but also result in a processor that provides improved application performance.
Several factors contributed to the popularity of CISC in the 1970s. In those days, memory was very expensive and small in capacity. Even in the mid-1970s, the price of a small 16 KB memory was about $500. So there was a need to minimize the amount of memory required to store a program. An implication of this requirement is that each processor instruction must do more, leading to complex instruction set designs. Complex instructions meant complex hardware, which was also expensive. This was a problem processor designers grappled with until Wilkes proposed microprogrammed control in the early 1950s.
Figure 1. The ISA-level architecture can be implemented either directly in hardware or through a microprogrammed control.
A microprogram is a small run-time interpreter that takes the complex instruction and generates a sequence of simple instructions that can be executed by the hardware. Thus the hardware need not be complex. Once it became possible to design such complex processors by using microprogrammed control, designers went crazy and tried to close the semantic gap between the instructions of the processor and high-level languages. This semantic gap refers to the fact that each instruction in a high-level language specifies a lot more work than an instruction in the machine language. Think of a while loop statement in a high-level language such as C, for example. If we have a processor instruction with the while loop semantics, we could just use one machine language instruction. This explains why most CISC designs use microprogrammed control, as shown in Figure 1.
RISC designs, on the other hand, eliminate the microprogram layer and use the hardware to directly execute instructions. Here is another reason why RISC processors can potentially give improved performance. One advantage of using microprogrammed control is that we can implement variations on the basic ISA architecture by simply modifying the microprogram; there is no need to change the underlying hardware. Thus it is possible to come up with cheaper versions as well as high-performance processors for the same family of processors.
References
- Guide to RISC Processors for Programmers and Engineers by Sivarama P. Dandamudi, Springer (2005), ISBN 0-387-21017-2.
Tuesday, 8 November 2016
Audio Processor Circuit using IC SSM2045
This audio processor circuit features the SSM2045 IC which was developed specially for electronic music applications and the 741 opamp IC. The circuit is configured as a low pass filter with a DC voltage control for gain. The input signal is set to a working level of 150mVpp through the resistor R1.
Audio Processor Circuit Diagram :
The filter has 2 buffered outputs: the 2-pole output at pin 1 and 4-pole output at pin 8. Internally, the outputs are connected to 2 voltage-controlled-amplifiers (VCA). The R15 and R16 are connected to these outputs to achieve optimum offset and control voltage suppression. P4 is the volume control. The current that flows to the pins 15 and 16 should not go beyond the maximum of 250 µA. The balance of the two VCAs and the entire filter is being controlled be a voltage range of -250 mV to + 250 mV at pin 14. This voltage can be set by P2.
The input can be driven with source impedances up to a maximum of 200 Ω. With an input level of 0dBm, the VCA weakens by 6 dB. The bias current needed at pin 17 is between 120 µA and 185 µA. The cutoff frequency can be shifted between 20 Hz and 20 kHz with a variable voltage at pin 5. This can be varied through P1. The capacitor values were selected to give the filter its Butterworth characteristics.
The output current of the SSM2045 IC is converted to a voltage output by the 741 opamp. Any sybsequent circuit must be DC decoupled from IC2. The noise-voltage ration is about 80 dB.